Lead CPU Design Verification Engineer
Job Title: Lead CPU Design Verification Engineer
Location: Hybrid
Employment Type: Full-time
About the Role
We are seeking an experienced Technical Lead to drive the verification strategy for our best-in-class RISC-V processors. Joining a team of world-class experts, you will architect advanced verification environments for complex Out-of-Order (OoO) subsystems and provide technical mentorship to the verification team. This is a technical leadership role focused on methodology and quality, without people management overhead.
Responsibilities
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Verification Strategy: Define and architect the verification strategy for complex CPU blocks, evaluating implementation costs and resource requirements.
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Environment Architecture: Architect scalable and reusable UVM testbenches and define golden reference models.
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Mentorship: Provide technical guidance to the verification team, conducting code reviews and enforcing best practices in UVM/SystemVerilog.
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Technical Planning: Define verification milestones, track progress against the schedule, and identify risks early.
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Cross-Functional Collaboration: Collaborate closely with Architecture and Design leads to ensure features are verifiable and specifications are clear.
Qualifications
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Bachelor’s, Master’s, or PhD in Electrical Engineering or Computer Science.
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8+ years of experience in verification of complex IPs or CPUs.
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Expert-level knowledge of SystemVerilog and UVM.
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Proven track record of defining verification methodologies for successful tape-outs.
Preferred Qualifications
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Deep understanding of Out-of-Order CPU architectures and memory hierarchies.
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Experience leading the verification of high-performance CPU cores.
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Deep knowledge of Formal Verification and when to apply it versus dynamic simulation.
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Experience with hardware emulation or FPGA prototyping.
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Contributions to the RISC-V community or open-source verification frameworks (e.g., CocoTB) are a plus.
Apply by sending your CV to: ana.matijevic@chipfy.ai