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Principal/Staff Design Verification Engineer
High-Performance RISC-V CPU, NoC and Memory Subsystem Verification
 

Job Title: Principal/Staff Design Verification Engineer

 Location: Hybrid

 Employment Type: Full-time
 

About the Role
 

We are looking for an experienced Principal/Staff Design Verification Engineer to join our team developing high-performance RISC-V processor IP.

This is a senior technical role offering the opportunity to take ownership of the verification of complex IP blocks, drive verification methodologies, and contribute to the development of next-generation processor architectures.

The ideal candidate has extensive hands-on experience verifying at least one of the following: CPU cores, Network-on-Chip (NoC), or memory subsystems. They should combine deep technical expertise with the ability to define verification strategies, solve complex verification challenges, and guide other engineers.

You will work closely with architecture, RTL design, and verification teams, contributing to the quality and robustness of high-performance processor IP.
 

Responsibilities:

  • Technical ownership of IP verification: Take end-to-end verification ownership of complex IP blocks, including CPU cores, NoC, or memory subsystems.

  • Verification strategy: Define, develop, and drive comprehensive verification strategies aligned with architectural specifications and project requirements.

  • Architecture analysis: Analyze microarchitecture specifications, identify potential corner cases, architectural ambiguities, and feature interactions.

  • Test plan development: Create, review, and maintain comprehensive verification plans, ensuring traceability between architectural requirements, test scenarios, and coverage.

  • Verification environment development: Architect, develop, and maintain scalable and reusable SystemVerilog/UVM-based verification environments.

  • Test development: Design and implement directed, constrained-random, and coverage-driven tests targeting complex scenarios and corner cases.

  • Coverage strategy and closure: Define functional coverage models, analyze code and functional coverage, identify verification gaps, and drive coverage closure.

  • Reference models and scoreboards: Develop and review architectural reference models, scoreboards, checkers, and other verification components.

  • Advanced debugging: Lead the investigation and resolution of complex RTL and testbench issues using industry-standard simulation and debugging tools.

  • Regression management: Define regression strategies, optimize simulation workflows, and ensure efficient and reliable verification execution.

  • Methodology development: Identify opportunities to improve verification methodologies, infrastructure, automation, and overall team productivity.

  • Cross-functional collaboration: Work closely with architecture, RTL design, formal verification, and software teams to resolve technical challenges and ensure design quality.

  • Technical leadership and mentoring: Provide technical guidance, mentor engineers, review verification implementations, and promote best engineering practices.

  • Verification accountability: Take full responsibility for verification quality, completeness, and sign-off readiness of assigned IPs.

​

IP Domains:

  • Candidates are expected to have strong hands-on verification experience in at least one of the following domains:

​

1. CPU Core Verification

  • Out-of-Order and In-Order CPU architectures.

  • Pipeline architecture and execution units.

  • Instruction fetch, decode, dispatch, issue, and retirement.

  • Branch prediction and speculative execution.

  • Exception handling, interrupts, and privileged architecture.

  • Floating-point, vector, SIMD, and atomic operations.

  • Memory ordering and architectural compliance.

  • ISA compliance and reference model integration.

​

2. NoC (Network-on-Chip) Verification

  • NoC architecture, topology, and routing algorithms.

  • AXI, CHI, TileLink, and other interconnect protocols.

  • Transaction routing, arbitration, and flow control.

  • Virtual channels, buffering, and congestion management.

  • Deadlock and livelock prevention.

  • Ordering, coherency, and protocol compliance.

  • Performance, bandwidth, and latency verification.

  • Error handling and fault injection.

​

3. Memory Subsystem Verification

  • L1, L2, and L3 cache architectures.

  • Cache coherency protocols (MESI, MOESI, etc.).

  • Memory controllers and memory interfaces.

  • Load/store units and memory pipelines.

  • Address translation, TLBs, and page tables.

  • Memory ordering and consistency models.

  • Atomic operations and synchronization primitives.

  • Cache replacement, prefetching, and writeback mechanisms.

  • AXI/CHI interfaces and memory transaction handling.

​

Requirements:

  • 8+ years of experience in semiconductor design verification, preferably at IP or SoC level.

  • Strong hands-on experience verifying at least one of the following: CPU, NoC, or memory subsystem IP.

  • Deep understanding of digital design and computer architecture.

  • Advanced knowledge of SystemVerilog and object-oriented programming concepts.

  • Strong proficiency in UVM and modern verification methodologies.

  • Experience defining and driving verification strategies for complex IPs.

  • Experience developing comprehensive test plans and functional coverage models.

  • Strong understanding of constrained-random verification and coverage-driven verification.

  • Experience developing scoreboards, reference models, checkers, and verification components.

  • Experience with industry-standard RTL simulators (Synopsys VCS, Cadence Xcelium, or Siemens Questa).

  • Proficiency with simulation debugging tools (Verdi, SimVision, or equivalent).

  • Experience with code coverage, functional coverage, and coverage closure.

  • Strong scripting skills in Python, SystemVerilog, and/or Bash.

  • Hands-on experience with Linux and Git.

  • Experience leading technical activities, reviewing code, and mentoring other engineers.

  • Ability to work independently, make technical decisions, and take ownership of complex verification challenges.

  • English language proficiency sufficient for technical communication and documentation.

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Desirable / Nice to Have:

  • Deep understanding of RISC-V architecture and ISA.

  • Experience with high-performance Out-of-Order CPU architectures.

  • Experience with AXI, ACE, CHI, TileLink, or other advanced interconnect protocols.

  • Experience with formal verification and assertion-based verification (SVA).

  • Experience with architectural reference models such as Spike, Sail, or custom models.

  • Experience with FPGA prototyping and post-silicon validation.

  • Experience with performance verification and performance modeling.

  • Experience with SystemVerilog DPI-C and C/C++ integration.

  • Experience developing verification infrastructure and automation frameworks.

  • Experience with AI-assisted verification methodologies and automated testbench generation.

​

Apply by sending your CV to: ana.matijevic@chipfy.ai

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